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<title>BNDSTX—Store Extended Bounds Using Address Translation </title></head>
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<h1>BNDSTX—Store Extended Bounds Using Address Translation</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>0F 1B /r BNDSTX mib, bnd</td>
<td>MR</td>
<td>V/V</td>
<td>MPX</td>
<td>Store the bounds in bnd and the pointer value in the index regis-ter of mib to a bound table entry (BTE) with address translation using the base of mib.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>
<p>Op/En</p>
<p>MR</p></td>
<td>
<p>Operand 1</p>
<p>SIB.base (r): Address of pointer</p>
<p>SIB.index(r)</p></td>
<td>
<p>Operand 2</p>
<p>ModRM:reg (r)</p></td>
<td>
<p>Operand 3</p>
<p>NA</p></td></tr></table>
<h2>Description</h2>
<p>BNDSTX uses the linear address constructed from the displacement and base register of the SIB-addressing form of the memory operand (mib) to perform address translation to store to a bound table entry. The bounds in the source operand bnd are written to the lower and upper bounds in the BTE. The content of the index register of mib is written to the pointer value field in the BTE.</p>
<p>This instruction does not cause memory access to the linear address of mib nor the effective address referenced by the base, and does not read or write any flags.</p>
<p>Segment overrides apply to the linear address computation with the base of mib, and are used during address translation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be linear address. There are no segmentation checks performed on the base of mib.</p>
<p>The base of mib will not be checked for canonical address violation as it does not access memory.</p>
<p>Any encoding of this instruction that does not specify base or index register will treat those registers as zero (constant). The reg-reg form of this instruction will remain a NOP.</p>
<p>The scale field of the SIB byte has no effect on these instructions and is ignored.</p>
<p>The bound register may be partially updated on memory faults. The order in which memory operands are loaded is implementation specific.</p>
<h2>Operation</h2>
<pre>base (cid:197) mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value (cid:197) mib.SIB.index ? mib.SIB.index : 0;</pre>
<p><strong>Outside 64-bit mode</strong></p>
<pre>A_BDE[31:0] (cid:197) (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );
A_BT[31:0] (cid:197) LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
    BNDSTATUS (cid:197) A_BDE | 02H;
    #BR;
FI;
A_DEST[31:0] (cid:197) (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 ); // address of Bound table entry
A_DEST[8][31:0] (cid:197) ptr_value;
A_DEST[0][31:0] (cid:197) BND.LB;
A_DEST[4][31:0] (cid:197) BND.UB;</pre>
<p><strong>In 64-bit mode</strong></p>
<pre>A_BDE[63:0] (cid:197) (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:20] «12 );<sup>1</sup>
A_BT[63:0] (cid:197) LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
    BNDSTATUS (cid:197) A_BDE | 02H;
    #BR;
FI;
A_DEST[63:0] (cid:197) (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 ); // address of Bound table entry
A_DEST[16][63:0] (cid:197) ptr_value;
A_DEST[0][63:0] (cid:197) BND.LB;
A_DEST[8][63:0] (cid:197) BND.UB;</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>BNDSTX: _bnd_store_ptr_bounds(const void **ptr_addr, const void *ptr_val);</p>
<h2>Flags Affected</h2>
<p>None</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#BR</td>
<td>If the bound directory entry is invalid.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 67H prefix is not used and CS.D=0.</p>
<p>If 67H prefix is used and CS.D=1.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>
<p>If a destination effective address of the Bound Table entry is outside the DS segment limit.</p>
<p>If DS register contains a NULL segment selector.</p>
<p>If the destination operand points to a non-writable segment</p></td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 16-bit addressing is used.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>If a destination effective address of the Bound Table entry is outside the DS segment limit.</td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 16-bit addressing is used.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>If a destination effective address of the Bound Table entry is outside the DS segment limit.</td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<p>1.</p>
<table class="exception-table">
<tr>
<td>If CPL &lt; 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumer-</td></tr>
<tr>
<td>ated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of <em>Intel® 64 and IA-32 Architectures Software Devel-</em></td></tr>
<tr>
<td><em>oper’s Manual, Volume 1</em>.</td></tr></table>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#BR</td>
<td>If the bound directory entry is invalid.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If ModRM is RIP relative.</p>
<p>If the LOCK prefix is used.</p>
<p>If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>
<p>If the memory address (A_BDE or A_BTE) is in a non-canonical form.</p>
<p>If the destination operand points to a non-writable segment</p></td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table></body></html>